1. Technical Field
The present disclosure relates to a method for manufacturing, on the same semiconductor wafer, areas of SOI (“Semiconductor-On-Insulator”) type, and solid substrate (bulk) areas.
2. Discussion of the Related Art
To improve the performance of MOS transistors carrying out the logic functions of an integrated circuit and to decrease their dimensions, a solution is to manufacture such MOS transistors inside and on top of a thin single-crystal semiconductor layer formed on an insulating layer laid on a single-crystal semiconductor substrate. The thin single-crystal semiconductor layer is then currently called “SOI layer”. A substrate or a semiconductor wafer coated with such an SOI layer will be called SOI substrate or wafer.
As technology develops, the minimum dimensions of transistors tend to be made smaller and smaller, with a gate length capable of being smaller than 20 nm, and the thickness of the SOI layer is correlatively decreased to values smaller than 10 nm, and even to values smaller than 5 nm. SOI layers with such a small thickness are not suited to the manufacturing of components capable of withstanding voltages higher than the voltages of logic components and/or of conducting higher currents than those implied in the operation of logic components, which, for example, occurs for electrostatic discharge protection devices. It is desirable to form these last components, here called “power components” to differentiate them from logic components, directly in a single-crystal semiconductor substrate.
It is thus desired to form a mixed or hybrid wafer comprising SOI-type areas suited to the forming of logic components, and bulk areas suited to the forming of power components. Further, for the manufacturing of components inside and on top of the SOI-type areas and inside and on top of the bulk areas, the upper surfaces of these areas should be as exactly as possible in a same plane, which especially enables carrying out optimized photolithography steps.
Known methods for forming such a hybrid wafer, such as described in U.S. Pat. No. 5,894,152, have various disadvantages. They are difficult to implement, need a large number of steps, and/or are not adapted to the case where the thickness of the SOI layer has a value smaller than 10 nm, or even smaller than 5 nm.